249 lines
6.4 KiB
Python
249 lines
6.4 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.structure import _Slice, _Assign
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from migen.fhdl.visit import NodeVisitor, NodeTransformer
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from migen.fhdl.bitcontainer import value_bits_sign
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from migen.util.misc import flat_iteration
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class _SignalLister(NodeVisitor):
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def __init__(self):
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self.output_list = set()
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def visit_Signal(self, node):
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self.output_list.add(node)
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class _TargetLister(NodeVisitor):
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def __init__(self):
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self.output_list = set()
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self.target_context = False
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def visit_Signal(self, node):
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if self.target_context:
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self.output_list.add(node)
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def visit_Assign(self, node):
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self.target_context = True
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self.visit(node.l)
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self.target_context = False
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def visit_ArrayProxy(self, node):
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for choice in node.choices:
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self.visit(choice)
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def list_signals(node):
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lister = _SignalLister()
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lister.visit(node)
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return lister.output_list
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def list_targets(node):
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lister = _TargetLister()
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lister.visit(node)
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return lister.output_list
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def _resort_statements(ol):
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return [statement for i, statement in
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sorted(ol, key=lambda x: x[0])]
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def group_by_targets(sl):
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groups = []
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seen = set()
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for order, stmt in enumerate(flat_iteration(sl)):
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targets = set(list_targets(stmt))
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group = [(order, stmt)]
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disjoint = targets.isdisjoint(seen)
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seen |= targets
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if not disjoint:
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groups, old_groups = [], groups
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for old_targets, old_group in old_groups:
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if targets.isdisjoint(old_targets):
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groups.append((old_targets, old_group))
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else:
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targets |= old_targets
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group += old_group
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groups.append((targets, group))
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return [(targets, _resort_statements(stmts))
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for targets, stmts in groups]
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def list_special_ios(f, ins, outs, inouts):
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r = set()
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for special in f.specials:
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r |= special.list_ios(ins, outs, inouts)
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return r
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class _ClockDomainLister(NodeVisitor):
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def __init__(self):
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self.clock_domains = set()
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def visit_ClockSignal(self, node):
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self.clock_domains.add(node.cd)
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def visit_ResetSignal(self, node):
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self.clock_domains.add(node.cd)
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def visit_clock_domains(self, node):
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for clockname, statements in node.items():
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self.clock_domains.add(clockname)
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self.visit(statements)
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def list_clock_domains_expr(f):
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cdl = _ClockDomainLister()
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cdl.visit(f)
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return cdl.clock_domains
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def list_clock_domains(f):
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r = list_clock_domains_expr(f)
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for special in f.specials:
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r |= special.list_clock_domains()
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for cd in f.clock_domains:
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r.add(cd.name)
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return r
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def is_variable(node):
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if isinstance(node, Signal):
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return node.variable
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elif isinstance(node, _Slice):
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return is_variable(node.value)
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elif isinstance(node, Cat):
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arevars = list(map(is_variable, node.l))
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r = arevars[0]
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for x in arevars:
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if x != r:
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raise TypeError
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return r
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else:
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raise TypeError
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def generate_reset(rst, sl):
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targets = list_targets(sl)
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return [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
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def insert_reset(rst, sl):
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return [If(rst, *generate_reset(rst, sl)).Else(*sl)]
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def insert_resets(f):
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newsync = dict()
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for k, v in f.sync.items():
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if f.clock_domains[k].rst is not None:
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newsync[k] = insert_reset(ResetSignal(k), v)
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else:
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newsync[k] = v
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f.sync = newsync
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class _Lowerer(NodeTransformer):
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def __init__(self):
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self.target_context = False
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self.extra_stmts = []
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self.comb = []
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def visit_Assign(self, node):
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old_target_context, old_extra_stmts = self.target_context, self.extra_stmts
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self.extra_stmts = []
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self.target_context = True
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lhs = self.visit(node.l)
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self.target_context = False
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rhs = self.visit(node.r)
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r = _Assign(lhs, rhs)
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if self.extra_stmts:
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r = [r] + self.extra_stmts
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self.target_context, self.extra_stmts = old_target_context, old_extra_stmts
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return r
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# Basics are FHDL structure elements that back-ends are not required to support
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# but can be expressed in terms of other elements (lowered) before conversion.
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class _BasicLowerer(_Lowerer):
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def __init__(self, clock_domains):
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self.clock_domains = clock_domains
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_Lowerer.__init__(self)
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def visit_ArrayProxy(self, node):
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# TODO: rewrite without variables
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array_muxed = Signal(value_bits_sign(node), variable=True)
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if self.target_context:
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k = self.visit(node.key)
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cases = {}
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for n, choice in enumerate(node.choices):
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cases[n] = [self.visit_Assign(_Assign(choice, array_muxed))]
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self.extra_stmts.append(Case(k, cases).makedefault())
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else:
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cases = dict((n, _Assign(array_muxed, self.visit(choice)))
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for n, choice in enumerate(node.choices))
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self.comb.append(Case(self.visit(node.key), cases).makedefault())
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return array_muxed
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def visit_ClockSignal(self, node):
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return self.clock_domains[node.cd].clk
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def visit_ResetSignal(self, node):
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return self.clock_domains[node.cd].rst
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class _ComplexSliceLowerer(_Lowerer):
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def visit_Slice(self, node):
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if not isinstance(node.value, Signal):
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slice_proxy = Signal(value_bits_sign(node.value))
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if self.target_context:
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a = _Assign(node.value, slice_proxy)
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else:
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a = _Assign(slice_proxy, node.value)
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self.comb.append(self.visit_Assign(a))
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node = _Slice(slice_proxy, node.start, node.stop)
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return NodeTransformer.visit_Slice(self, node)
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def _apply_lowerer(l, f):
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f = l.visit(f)
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f.comb += l.comb
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for special in f.specials:
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for obj, attr, direction in special.iter_expressions():
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if direction != SPECIAL_INOUT:
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# inouts are only supported by Migen when connected directly to top-level
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# in this case, they are Signal and never need lowering
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l.comb = []
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l.target_context = direction != SPECIAL_INPUT
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l.extra_stmts = []
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expr = getattr(obj, attr)
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expr = l.visit(expr)
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setattr(obj, attr, expr)
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f.comb += l.comb + l.extra_stmts
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return f
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def lower_basics(f):
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return _apply_lowerer(_BasicLowerer(f.clock_domains), f)
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def lower_complex_slices(f):
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return _apply_lowerer(_ComplexSliceLowerer(), f)
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class _ClockDomainRenamer(NodeVisitor):
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def __init__(self, old, new):
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self.old = old
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self.new = new
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def visit_ClockSignal(self, node):
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if node.cd == self.old:
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node.cd = self.new
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def visit_ResetSignal(self, node):
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if node.cd == self.old:
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node.cd = self.new
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def rename_clock_domain_expr(f, old, new):
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cdr = _ClockDomainRenamer(old, new)
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cdr.visit(f)
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def rename_clock_domain(f, old, new):
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rename_clock_domain_expr(f, old, new)
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if new in f.sync:
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f.sync[new].extend(f.sync[old])
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else:
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f.sync[new] = f.sync[old]
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del f.sync[old]
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for special in f.specials:
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special.rename_clock_domain(old, new)
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try:
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cd = f.clock_domains[old]
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except KeyError:
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pass
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else:
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cd.rename(new)
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