Gabriel Somlo a0dad1b071 soc_core: additional CSR safety assertions ... Since csr_data_width=64 has probably never worked properly, remove it as one of the possible options (to be fixed and re-added later). Add csr_data_width=16, which has been tested and does work. Additionally, ensure csr_data_width <= csr_alignment (we should not attempt to create (sub)registers larger than the CPU's native word size or XLen). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>		2019-12-12 13:14:16 -05:00
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cores	cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)	2019-12-09 19:25:38 +01:00
integration	soc_core: additional CSR safety assertions	2019-12-12 13:14:16 -05:00
interconnect	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
software	soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32	2019-11-18 09:00:19 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00