75 lines
2.4 KiB
Python
75 lines
2.4 KiB
Python
from migen.fhdl.structure import *
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def handler(memory, ns, clk):
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r = ""
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gn = ns.get_name
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adrbits = bits_for(memory.depth-1)
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(memory) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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adr_regs = {}
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data_regs = {}
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST and port.we is not None:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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r += "always @(posedge " + gn(clk) + ") begin\n"
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for port in memory.ports:
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if port.we is not None:
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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if port.mode == WRITE_FIRST and port.we is not None:
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST or port.we is None:
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rd = "\t" + bassign
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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for port in memory.ports:
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST and port.we is not None:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += "\n"
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if memory.init is not None:
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r += "initial begin\n"
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for i, c in enumerate(memory.init):
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r += "\t" + gn(memory) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n"
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r += "end\n\n"
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return r
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