Sebastien Bourdeauducq a1fc86af8f flow: fix actor repr		2012-06-07 15:48:35 +02:00
..
actorlib	flow: refactor scheduling models	2012-06-07 14:44:43 +02:00
bank	bank/description: pad unaligned multi-word registers at the top	2012-05-21 22:55:23 +02:00
bus	bus/wishbone2asmi: fix cache tag size	2012-05-15 15:18:03 +02:00
corelogic	corelogic/roundrobin: handle correctly special case with 1 request source	2012-03-31 18:01:40 +02:00
fhdl	fhdl/verilog: add option to display which comb blocks are run	2012-04-30 16:38:40 -05:00
flow	flow: fix actor repr	2012-06-07 15:48:35 +02:00
sim	sim: pass extra keyword arguments to Verilog converter	2012-04-30 16:38:17 -05:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00