Sebastien Bourdeauducq
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a1fc86af8f
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flow: fix actor repr
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2012-06-07 15:48:35 +02:00 |
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Sebastien Bourdeauducq
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680a34465d
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flow: refactor scheduling models
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2012-06-07 14:44:43 +02:00 |
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Sebastien Bourdeauducq
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493b181af1
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bank/description: pad unaligned multi-word registers at the top
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2012-05-21 22:55:23 +02:00 |
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Sebastien Bourdeauducq
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9449bbea0a
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Add LICENSE file
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2012-05-21 19:56:23 +02:00 |
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Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
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Sebastien Bourdeauducq
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0bea1e2589
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asmi: dat_wm high to disable data write
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2012-05-15 14:41:54 +02:00 |
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Sebastien Bourdeauducq
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f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
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398ece8fe2
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fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
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2012-04-30 16:38:40 -05:00 |
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Sebastien Bourdeauducq
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0b62e573ae
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sim: pass extra keyword arguments to Verilog converter
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2012-04-30 16:38:17 -05:00 |
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Sebastien Bourdeauducq
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6a52e44d09
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fhdl: support len() on signals
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2012-04-08 18:06:22 +02:00 |
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Sebastien Bourdeauducq
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b9c533be51
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bank/csrgen: allow specifying existing CSR interface
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2012-04-06 14:59:09 +02:00 |
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Sebastien Bourdeauducq
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2a4e49e381
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fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
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Sebastien Bourdeauducq
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623e8e436a
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fhdl/verilog: do not attempt to initialize instance and mem output signals
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2012-04-02 12:59:42 +02:00 |
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Sebastien Bourdeauducq
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6e3b25ebb6
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
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Sebastien Bourdeauducq
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d3c6b8d16f
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sim/proxy: support lists
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2012-04-01 17:19:53 +02:00 |
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Sebastien Bourdeauducq
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f3ae22f488
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fhdl/verilog: initialize internal read-only signals with their reset values
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2012-04-01 16:39:11 +02:00 |
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Sebastien Bourdeauducq
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0dfc215fe8
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corelogic/roundrobin: handle correctly special case with 1 request source
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2012-03-31 18:01:40 +02:00 |
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Sebastien Bourdeauducq
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94b02aa8ed
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bus/asmicon: initiator
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2012-03-30 22:16:31 +02:00 |
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Sebastien Bourdeauducq
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bb864c65dc
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sim: proxy
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2012-03-30 16:40:26 +02:00 |
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Sebastien Bourdeauducq
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081b658e2d
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Update copyright notices
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2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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d47b564fad
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corelogic/fsm: typo
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2012-03-18 22:12:46 +01:00 |
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Sebastien Bourdeauducq
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5f28103769
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corelogic/fsm: delayed enters
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2012-03-18 00:09:40 +01:00 |
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Sebastien Bourdeauducq
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a4294762d0
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corelogic/roundrobin: CE switching
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2012-03-16 16:54:47 +01:00 |
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Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
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Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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Sebastien Bourdeauducq
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bfcd4e636b
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fhdl: handle negative constants correctly
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2012-03-08 20:49:24 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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678a89d572
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sim: fix zero encoding
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2012-03-08 15:34:08 +01:00 |
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Sebastien Bourdeauducq
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decbd069fa
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sim: fix message debug formatting
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2012-03-08 15:27:35 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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db8f8bf2e3
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fhdl: register memory objects with namespace
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2012-03-06 18:33:44 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
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sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
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90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
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Sebastien Bourdeauducq
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9da512dbf5
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sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
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Sebastien Bourdeauducq
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22b3c11b93
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sim: clean startup/shutdown
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2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
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06de17b16c
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sim: remove temporary files and socket
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2012-03-06 14:20:26 +01:00 |
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Sebastien Bourdeauducq
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7230508e7c
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fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
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2012-03-06 14:18:22 +01:00 |
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Sebastien Bourdeauducq
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2c375e900f
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sim: remove default sockaddr
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2012-03-06 13:58:49 +01:00 |
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Sebastien Bourdeauducq
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8d16fde48c
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fhdl: add simulation functions in fragment
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2012-03-06 13:58:22 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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29859acc34
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sim: two way IPC working
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2012-03-04 19:17:03 +01:00 |
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Sebastien Bourdeauducq
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8586daf2dd
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sim: IPC module (lacks str/int encoding)
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2012-03-03 18:55:38 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
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d8d4e81b6e
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bank/csrgen: fix RE generation
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2012-02-18 18:56:18 +01:00 |
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Sebastien Bourdeauducq
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55a265d967
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bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |
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Sebastien Bourdeauducq
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92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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Sebastien Bourdeauducq
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f995e8b92e
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fhdl: check we pass BV to signals
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2012-02-17 23:50:54 +01:00 |
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Sebastien Bourdeauducq
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a1ad30faab
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fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |