litex/litex
Florent Kermarrec a27385a79c soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
..
boards targets/kcu105: move cd_pll4x. 2020-03-10 17:02:28 +01:00
build build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends) 2020-03-09 19:02:23 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
tools Fix copyrights 2020-03-05 17:44:10 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00