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a55fee78d2
litex
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migen
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corelogic
History
Sebastien Bourdeauducq
43653dbe1a
corelogic: reorder buffer (untested)
2012-07-12 18:33:28 +02:00
..
__init__.py
corelogic: round-robin module
2011-12-08 21:15:02 +01:00
buffers.py
corelogic: reorder buffer (untested)
2012-07-12 18:33:28 +02:00
divider.py
Use meaningful class names
2012-01-20 23:07:32 +01:00
fsm.py
corelogic/fsm: typo
2012-03-18 22:12:46 +01:00
misc.py
fhdl: arrays (TODO: use correct BV for intermediate signals)
2012-07-09 15:16:38 +02:00
record.py
corelogic/record: better repr
2012-06-08 17:49:31 +02:00
roundrobin.py
corelogic/roundrobin: handle correctly special case with 1 request source
2012-03-31 18:01:40 +02:00