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litex/migen/fhdl
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Sebastien Bourdeauducq eed8fa374d fhdl/arrays: use correct BV for intermediate signals 2012-07-11 12:06:32 +02:00
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__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
autofragment.py Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
namer.py fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00
structure.py fhdl: arrays (TODO: use correct BV for intermediate signals) 2012-07-09 15:16:38 +02:00
tools.py fhdl/arrays: use correct BV for intermediate signals 2012-07-11 12:06:32 +02:00
tracer.py fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00
verilog.py fhdl: arrays (TODO: use correct BV for intermediate signals) 2012-07-09 15:16:38 +02:00
verilog_mem_behavioral.py fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00