litex/migen
Sebastien Bourdeauducq a67f483f0f Token: support idle_wait 2012-12-14 19:16:22 +01:00
..
actorlib Token: support idle_wait 2012-12-14 19:16:22 +01:00
bank migen/bank: do not create interface in default param 2012-12-06 17:28:28 +01:00
bus elsewhere: do not create interface in default param 2012-12-06 17:34:48 +01:00
corelogic corelogic/roundrobin: fix request width (again) 2012-11-29 23:47:51 +01:00
fhdl fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
flow Token: support idle_wait 2012-12-14 19:16:22 +01:00
pytholite Token: support idle_wait 2012-12-14 19:16:22 +01:00
sim New specification for width and signedness 2012-11-29 21:22:38 +01:00
uio Move Token to migen.flow.transactions 2012-12-14 15:55:38 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00