101 lines
2.4 KiB
Python
101 lines
2.4 KiB
Python
from migen.fhdl.structure import *
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from migen.bus.simple import *
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from migen.bus.transactions import *
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from migen.sim.generic import PureSimulable
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from migen.bank.description import RegisterField
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data_width = 8
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class Interface(SimpleInterface):
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def __init__(self):
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super().__init__(Description(
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(M_TO_S, "adr", 14),
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(M_TO_S, "we", 1),
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(M_TO_S, "dat_w", data_width),
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(S_TO_M, "dat_r", data_width)))
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class Interconnect(SimpleInterconnect):
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pass
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class Initiator(PureSimulable):
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def __init__(self, generator, bus=None):
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self.generator = generator
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if bus is None:
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bus = Interface()
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self.bus = bus
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self.transaction = None
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self.done = False
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def do_simulation(self, s):
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if not self.done:
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if self.transaction is not None:
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if isinstance(self.transaction, TRead):
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self.transaction.data = s.rd(self.bus.dat_r)
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else:
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s.wr(self.bus.we, 0)
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.transaction = None
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self.done = True
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if self.transaction is not None:
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s.wr(self.bus.adr, self.transaction.address)
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if isinstance(self.transaction, TWrite):
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s.wr(self.bus.we, 1)
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s.wr(self.bus.dat_w, self.transaction.data)
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def _compute_page_bits(nwords):
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npages = (nwords - 1)//512
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if npages > 0:
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return bits_for(npages-1)
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else:
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return 0
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class SRAM:
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def __init__(self, mem_or_size, address, bus=None):
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(data_width, mem_or_size//(data_width//8))
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self.address = address
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page_bits = _compute_page_bits(self.mem.depth)
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if page_bits:
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self._page = RegisterField("page", page_bits)
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else:
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self._page = None
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if bus is None:
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bus = Interface()
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self.bus = bus
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def get_registers(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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def get_fragment(self):
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port = self.mem.get_port(write_capable=True)
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sel = Signal()
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sel_r = Signal()
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sync = [sel_r.eq(sel)]
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comb = [
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sel.eq(self.bus.adr[9:] == self.address),
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port.we.eq(sel & self.bus.we),
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port.dat_w.eq(self.bus.dat_w),
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If(sel_r,
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self.bus.dat_r.eq(port.dat_r)
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)
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]
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if self._page is None:
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comb.append(port.adr.eq(self.bus.adr[:len(port.adr)]))
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else:
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pv = self._page.field.r
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comb.append(port.adr.eq(Cat(self.bus.adr[:len(port.adr)-len(pv)], pv)))
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return Fragment(comb, sync, memories=[self.mem])
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