442 lines
12 KiB
Python
442 lines
12 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.corelogic.misc import optree
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class Term:
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def __init__(self, width, pipe=False):
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self.width = width
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self.pipe = pipe
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self.i = Signal(BV(self.width))
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self.t = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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frag = [
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self.o.eq(self.i==self.t)
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]
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if self.pipe:
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return Fragment(sync=frag)
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else:
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return Fragment(comb=frag)
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class RangeDetector:
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def __init__(self, width, pipe=False):
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self.width = width
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self.pipe = pipe
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self.i = Signal(BV(self.width))
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self.low = Signal(BV(self.width))
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self.high = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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frag = [
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self.o.eq((self.i >= self.low) & ((self.i <= self.high)))
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]
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if self.pipe:
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return Fragment(sync=frag)
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else:
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return Fragment(comb=frag)
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class EdgeDetector:
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def __init__(self, width, pipe=False, mode = "RFB"):
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self.width = width
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self.pipe = pipe
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self.mode = mode
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self.i = Signal(BV(self.width))
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self.i_d = Signal(BV(self.width))
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if "R" in mode:
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self.r_mask = Signal(BV(self.width))
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self.ro = Signal()
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if "F" in mode:
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self.f_mask = Signal(BV(self.width))
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self.fo = Signal()
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if "B" in mode:
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self.b_mask = Signal(BV(self.width))
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self.bo = Signal()
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self.o = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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sync += [self.i_d.eq(self.i)]
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# Rising Edge
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if "R" in self.mode:
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r_eq = [self.ro.eq(self.r_mask & self.i & (~self.i_d))]
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if self.pipe:
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sync += r_eq
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else:
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comb += r_eq
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else:
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comb += [self.ro.eq(0)]
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# Falling Edge
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if "F" in self.mode:
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f_eq = [self.fo.eq(self.f_mask & (~ self.i) & self.i_d)]
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if self.pipe:
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sync += f_eq
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else:
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comb += f_eq
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else:
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comb += [self.fo.eq(0)]
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# Both
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if "B" in self.mode:
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b_eq = [self.bo.eq(self.b_mask & self.i != self.i_d)]
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if self.pipe:
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sync += b_eq
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else:
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comb += b_eq
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else:
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comb += [self.bo.eq(0)]
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#Output
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comb += [self.o.eq(self.ro | self.fo | self.bo)]
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return Fragment(comb, sync)
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class Timer:
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def __init__(self, width):
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self.width = width
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self.start = Signal()
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self.stop = Signal()
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self.clear = Signal()
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self.enable = Signal()
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self.cnt = Signal(BV(self.width))
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self.cnt_max = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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sync += [
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If(self.stop,
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self.enable.eq(0),
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self.cnt.eq(0),
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self.o.eq(0)
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).Elif(self.clear,
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self.cnt.eq(0),
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self.o.eq(0)
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).Elif(self.start,
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self.enable.eq(1)
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).Elif(self.enable,
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If(self.cnt <= self.cnt_max,
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self.cnt.eq(self.cnt+1)
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).Else(
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self.o.eq(1)
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)
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),
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If(self.enable,
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self.enable.eq(0),
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self.cnt.eq(0)
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).Elif(self.clear,
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self.cnt.eq(0)
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).Elif(self.start,
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self.enable.eq(1)
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)
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]
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return Fragment(comb, sync)
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class Sum:
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def __init__(self,width=4,pipe=False):
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self.width = width
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self.pipe = pipe
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self.i = Signal(BV(self.width))
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self._o = Signal()
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self.o = Signal()
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self._lut_port = MemoryPort(adr=self.i, dat_r=self._o)
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self.prog = Signal()
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self.prog_adr = Signal(BV(width))
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self.prog_dat = Signal()
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self._prog_port = MemoryPort(adr=self.prog_adr, we=self.prog, dat_w=self.prog_dat)
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self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)
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def get_fragment(self):
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comb = []
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sync = []
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memories = [self._mem]
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if self.pipe:
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sync += [self.o.eq(self._o)]
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else:
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comb += [self.o.eq(self._o)]
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return Fragment(comb=comb,sync=sync,memories=memories)
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class Trigger:
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def __init__(self,address, trig_width, dat_width, ports):
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self.address = address
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self.trig_width = trig_width
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self.dat_width = dat_width
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self.ports = ports
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assert (len(self.ports) <= 4), "Nb Ports > 4 (This version support 4 ports Max)"
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self._sum = Sum(len(self.ports))
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self.in_trig = Signal(BV(self.trig_width))
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self.in_dat = Signal(BV(self.dat_width))
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self.hit = Signal()
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self.dat = Signal(BV(self.dat_width))
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# Csr interface
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for i in range(len(self.ports)):
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if isinstance(self.ports[i],Term):
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setattr(self,"_term_reg%d"%i,RegisterField("rst", 1*self.trig_width, reset=0,
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access_bus=WRITE_ONLY, access_dev=READ_ONLY))
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elif isinstance(self.ports[i],EdgeDetector):
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setattr(self,"_edge_reg%d"%i,RegisterField("rst", 3*self.trig_width, reset=0,
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access_bus=WRITE_ONLY, access_dev=READ_ONLY))
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elif isinstance(self.ports[i],RangeDetector):
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setattr(self,"_range_reg%d"%i,RegisterField("rst", 2*self.trig_width, reset=0,
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access_bus=WRITE_ONLY, access_dev=READ_ONLY))
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self._sum_reg = RegisterField("_sum_reg", 17, reset=0,access_bus=WRITE_ONLY, access_dev=READ_ONLY)
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regs = []
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objects = self.__dict__
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for object in objects:
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if "_reg" in object:
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regs.append(objects[object])
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regs.append(self._sum_reg)
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self.bank = csrgen.Bank(regs,address=address)
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def get_fragment(self):
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comb = []
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sync = []
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# Connect in_trig to input of trig elements
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comb+= [port.i.eq(self.in_trig) for port in self.ports]
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# Connect output of trig elements to sum
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# Todo : Add sum tree to have more that 4 inputs
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comb+= [self._sum.i[j].eq(self.ports[j].o) for j in range(len(self.ports))]
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# Connect sum ouput to hit
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comb+= [self.hit.eq(self._sum.o)]
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# Add ports & sum to frag
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frag = self.bank.get_fragment()
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frag += self._sum.get_fragment()
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for port in self.ports:
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frag += port.get_fragment()
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comb+= [self.dat.eq(self.in_dat)]
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#Connect Registers
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for i in range(len(self.ports)):
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if isinstance(self.ports[i],Term):
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comb += [self.ports[i].t.eq(getattr(self,"_term_reg%d"%i).field.r[0:self.trig_width])]
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elif isinstance(self.ports[i],EdgeDetector):
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comb += [self.ports[i].r_mask.eq(getattr(self,"_edge_reg%d"%i).field.r[0:1*self.trig_width])]
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comb += [self.ports[i].f_mask.eq(getattr(self,"_edge_reg%d"%i).field.r[1*self.trig_width:2*self.trig_width])]
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comb += [self.ports[i].b_mask.eq(getattr(self,"_edge_reg%d"%i).field.r[2*self.trig_width:3*self.trig_width])]
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elif isinstance(self.ports[i],RangeDetector):
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comb += [self.ports[i].low.eq(getattr(self,"_range_reg%d"%i).field.r[0:1*self.trig_width])]
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comb += [self.ports[i].high.eq(getattr(self,"_range_reg%d"%i).field.r[1*self.trig_width:2*self.trig_width])]
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comb += [
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self._sum.prog_dat.eq(self._sum_reg.field.r[0:16]),
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self._sum.prog.eq(self._sum_reg.field.r[16]),
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]
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return frag + Fragment(comb=comb, sync=sync)
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class Storage:
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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#Control
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self.rst = Signal()
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self.start = Signal()
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self.offset = Signal(BV(self.depth_width))
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self.size = Signal(BV(self.depth_width))
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self.done = Signal()
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#Write Path
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self.put = Signal()
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self.put_dat = Signal(BV(self.width))
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self._put_cnt = Signal(BV(self.depth_width))
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self._put_ptr = Signal(BV(self.depth_width))
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self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
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#Read Path
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self.get = Signal()
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self.get_dat = Signal(BV(self.width))
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self._get_cnt = Signal(BV(self.depth_width))
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self._get_ptr = Signal(BV(self.depth_width))
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self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
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#Others
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self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
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def get_fragment(self):
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comb = []
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sync = []
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memories = [self._mem]
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size_minus_offset = Signal(BV(self.depth_width))
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comb += [size_minus_offset.eq(self.size-self.offset)]
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#Control
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sync += [
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If(self.rst,
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self._put_cnt.eq(0),
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self._put_ptr.eq(0),
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self._get_cnt.eq(0),
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self._get_ptr.eq(0),
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self.done.eq(0)
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).Elif(self.start,
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self._put_cnt.eq(0),
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self._get_cnt.eq(0),
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self._get_ptr.eq(self._put_ptr-size_minus_offset)
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),
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If(self.put,
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self._put_cnt.eq(self._put_cnt+1),
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self._put_ptr.eq(self._put_ptr+1)
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),
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If(self.get,
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self._get_cnt.eq(self._get_cnt+1),
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self._get_ptr.eq(self._get_ptr+1)
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)
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]
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comb += [
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If(self._put_cnt == size_minus_offset-1,
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self.done.eq(1)
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).Elif(self._get_cnt == size_minus_offset-1,
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self.done.eq(1)
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).Else(
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self.done.eq(0)
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)
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]
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return Fragment(comb=comb, sync=sync, memories=memories)
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class Sequencer:
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def __init__(self,depth):
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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# Controller interface
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self.ctl_rst = Signal()
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self.ctl_offset = Signal(BV(self.depth_width))
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self.ctl_size = Signal(BV(self.depth_width))
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self.ctl_arm = Signal()
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self.ctl_done = Signal()
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# Triggers interface
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self.trig_hit = Signal()
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# Recorder interface
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self.rec_offset = Signal(BV(self.depth_width))
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self.rec_size = Signal(BV(self.depth_width))
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self.rec_start = Signal()
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self.rec_done = Signal()
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# Others
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self.enable = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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#Control
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sync += [
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If(self.ctl_rst,
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self.enable.eq(0)
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).Elif(self.ctl_arm,
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self.enable.eq(1)
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).Elif(self.rec_done,
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self.enable.eq(0)
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)
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]
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comb += [
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self.rec_offset.eq(self.ctl_offset),
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self.rec_size.eq(self.ctl_size),
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self.rec_start.eq(self.enable & self.trig_hit),
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self.ctl_done.eq(~self.enable)
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]
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return Fragment(comb=comb, sync=sync)
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class Recorder:
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def __init__(self,address, width, depth):
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self.address = address
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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self.storage = Storage(self.width, self.depth)
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self.sequencer = Sequencer(self.depth)
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# Csr interface
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self._rst = RegisterField("rst", reset=1)
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self._arm = RegisterField("arm", reset=0)
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self._done = RegisterField("done", reset=0, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._size = RegisterField("size", self.depth_width, reset=1)
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self._offset = RegisterField("offset", self.depth_width, reset=1)
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self._get = RegisterField("get", reset=1)
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self._get_dat = RegisterField("get_dat", self.width, reset=1,access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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regs = [self._rst, self._arm, self._done,
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self._size, self._offset,
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self._get, self._get_dat]
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self.bank = csrgen.Bank(regs,address=address)
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# Trigger Interface
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self.trig_hit = Signal()
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self.trig_dat = Signal(BV(self.width))
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def get_fragment(self):
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comb = []
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sync = []
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#Bank <--> Storage / Sequencer
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comb += [
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self.sequencer.ctl_rst.eq(self._rst.field.r),
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self.storage.rst.eq(self._rst.field.r),
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self.sequencer.ctl_offset.eq(self._offset.field.r),
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self.sequencer.ctl_size.eq(self._size.field.r),
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self.sequencer.ctl_arm.eq(self._arm.field.r),
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self._done.field.w.eq(self.sequencer.ctl_done)
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]
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#Storage <--> Sequencer <--> Trigger
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comb += [
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self.storage.offset.eq(self.sequencer.rec_offset),
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self.storage.size.eq(self.sequencer.rec_size),
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self.storage.start.eq(self.sequencer.rec_start),
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self.sequencer.rec_done.eq(self.storage.done),
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self.sequencer.trig_hit.eq(self.trig_hit),
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self.storage.put.eq(self.sequencer.enable),
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self.storage.put_dat.eq(self.trig_dat)
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]
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return self.bank.get_fragment()+\
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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Fragment(comb=comb, sync=sync)
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class MigCon:
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pass
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class MigLa:
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pass
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class MigIo:
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def __init__(self, width, mode = "IO"):
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self.width = width
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self.mode = mode
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self.ireg = description.RegisterField("i", 0, READ_ONLY, WRITE_ONLY)
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self.oreg = description.RegisterField("o", 0)
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if "I" in self.mode:
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self.inputs = Signal(BV(self.width))
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self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
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self.ireg.field.w.name_override = "inputs"
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if "O" in self.mode:
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self.outputs = Signal(BV(self.width))
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self.oreg = description.RegisterField("o", self.width)
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self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg])
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def get_fragment(self):
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return self.bank.get_fragment()
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