litex/sim/tb_spi2Csr.py

10 lines
165 B
Python

from migen.fhdl.structure import *
from migen.fhdl import verilog, autofragment
import sys
sys.path.append("../")
import spi2Csr
spi2csr0 = spi2Csr.Spi2Csr(16,8)