Florent Kermarrec a8ddbb190a cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).		2020-12-30 14:41:54 +01:00
..
boards	targets/arty: add variant support through --variant argument.	2020-12-29 18:45:41 +01:00
build	Quartus: handle vh and svh files	2020-12-20 11:53:08 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).	2020-12-30 14:41:54 +01:00
tools	tools/litex_json2dts/soc_controller: remove VexRiscv-SMP workaround now that we able to use upstream linux litex patches.	2020-12-29 12:25:38 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00