cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).
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@ -19,7 +19,8 @@ import os
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CPU_VARIANTS = {
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"linux": "VexRiscv",
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"standard": "VexRiscv",
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"linux": "VexRiscv", # Similar to standard.
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}
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class Open(Signal): pass
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