Sebastien Bourdeauducq f995e8b92e fhdl: check we pass BV to signals		2012-02-17 23:50:54 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	fhdl/namer: Add support for STORE_DEREF opcode	2012-02-02 21:15:10 +01:00
structure.py	fhdl: check we pass BV to signals	2012-02-17 23:50:54 +01:00
tools.py	fhdl: support forwarding of bidirectional signals from instance ports	2012-02-16 18:34:32 +01:00
verilog.py	fhdl/verilog: properly connect instance inouts	2012-02-17 11:08:41 +01:00
verilog_mem_behavioral.py	fhdl: support memory read enable	2012-01-27 21:39:23 +01:00