Florent Kermarrec b057858071 gen/fhdl/verilog: explicitly define input/output/inout wires. ... When integrating designs which set `default_nettype none, the top also needs to explicitly define the type of the signals.		2020-05-05 16:58:33 +02:00
..
fhdl	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
sim	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
__init__.py	gen: add common with reverse_bits/reverse_bytes functions	2018-10-30 10:15:29 +01:00
common.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
io.py	litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.	2020-04-10 08:47:07 +02:00