litex/litex
2018-10-18 13:42:51 +02:00
..
boards platforms/kc705: add ddram_dual_rank 2018-10-09 15:39:03 +02:00
build build/xilinx/vivado: enable xpm libraries 2018-10-18 09:25:34 +02:00
gen build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
soc bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
__init__.py ease RemoteClient import 2018-09-23 10:23:00 +02:00