Florent Kermarrec ab80606036 soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.		2020-05-27 18:40:45 +02:00
..
boards	targets/nexys4ddr: update add_sdcard method.	2020-05-27 14:09:05 +02:00
build	tools: add litex_jtag_uart to create a virtual uart for the jtag uart.	2020-05-25 10:21:06 +02:00
gen	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
soc	soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.	2020-05-27 18:40:45 +02:00
tools	tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM.	2020-05-27 15:16:30 +02:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00