litex/litex/soc
Florent Kermarrec ae45be4773 soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL 2020-02-18 10:15:01 +01:00
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cores soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL 2020-02-18 10:15:01 +01:00
doc doc: fix regression with new irq manager 2020-02-13 08:32:44 +08:00
integration soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) 2020-02-18 09:13:32 +01:00
interconnect soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) 2020-02-18 09:13:32 +01:00
software bios/boot: update and fix flashboot, improve verbosity 2020-02-17 19:21:54 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00