Florent Kermarrec af52203c00 soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state		2019-11-17 11:57:14 +01:00
..
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
axi.py	soc/interconnect/axi: re-align to improve readability	2019-10-11 08:41:05 +02:00
csr.py	csr: add we signal to CSR, CSRStatus	2019-09-24 17:51:06 +02:00
csr_bus.py	change >512 B CSR memory exception to a warning	2019-11-15 15:34:12 +01:00
csr_eventmanager.py	csr_eventmanager: add name and description args	2019-09-19 17:23:03 +08:00
packet.py	soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state	2019-11-17 11:57:14 +01:00
stream.py	soc/interconnect/stream: add separators, mode Actor modules just after Endpoint	2019-09-30 23:33:25 +02:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	interconnect/wishbone: fix Converter case when buses are identical	2019-10-11 21:49:11 +02:00
wishbone2csr.py	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)	2019-09-24 17:55:29 +02:00
wishbonebridge.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00