Sebastien Bourdeauducq b18cffb5e8 xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior		2013-07-04 23:49:12 +02:00
..
platforms	platforms/mixxeo: remove bank 3 DVI inputs	2013-07-04 19:27:28 +02:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	Call finalize() after CRG creation	2013-07-04 19:49:39 +02:00
crg.py	Use migen.fhdl.std	2013-05-26 18:07:26 +02:00
generic_platform.py	Call finalize() after CRG creation	2013-07-04 19:49:39 +02:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior	2013-07-04 23:49:12 +02:00