Sebastien Bourdeauducq b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method" ... This reverts commit 95cfc444e6.		2015-03-30 19:41:04 +08:00
..
actorlib	move dma_lasmi to MiSoC	2015-03-02 08:23:02 +01:00
bank
bus
fhdl	Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"	2015-03-30 19:41:04 +08:00
flow
genlib	migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)	2015-03-18 14:41:43 +01:00
sim	migen: create VerilogConvert and EDIFConvert classes and return it with convert functions	2015-03-30 11:37:55 +02:00
test	test_actor: add unittests for SimActor	2015-03-21 10:02:10 +01:00
util
__init__.py