litex/litex
2021-07-15 16:48:24 +02:00
..
build Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_options 2021-07-15 12:18:01 +02:00
compat Replace deprecated inspect.getargspec with inspect.getfullargspec. 2021-06-15 08:03:11 -05:00
gen gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
soc clock/gowin_gw1n: Add Initial On-Chip Oscillator support. 2021-07-14 11:42:35 +02:00
tools tools/litex_sim: Let the SDRAMPHYModel pick default settings. 2021-07-08 09:09:57 +02:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00