bunnie b3f9aa11be add option for BUFGCE to the clock generator buffer types		2020-01-24 14:58:51 +08:00
..
cores	add option for BUFGCE to the clock generator buffer types	2020-01-24 14:58:51 +08:00
integration	SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map)	2020-01-17 12:45:23 +01:00
interconnect	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
software	bios/sdram: switch to updated CSR accessors, and misc. cleanup	2020-01-13 10:09:02 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00