litex/litex/soc/integration
2020-01-17 12:45:23 +01:00
..
__init__.py
builder.py soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so 2019-12-31 09:58:26 +01:00
common.py
doc.py
export.py software, integration/export: rename and reimplement CSR accessors 2020-01-13 10:09:02 -05:00
soc_core.py SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user 2020-01-17 12:16:08 +01:00
soc_sdram.py SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) 2020-01-17 12:45:23 +01:00
soc_zynq.py