101 lines
3.1 KiB
Python
101 lines
3.1 KiB
Python
from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from miscope.uart2wishbone import UART2Wishbone
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from misoclib import identifier
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from lib.sata.k7sataphy import K7SATAPHY
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166.66MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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]
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class UART2WB(Module):
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csr_base = 0x00000000
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csr_data_width = 8
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csr_map = {
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"uart2wb": 0,
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"identifier": 2,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.uart2wb.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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# CSR
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self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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class TestDesign(UART2WB):
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default_platform = "kc705"
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def __init__(self, platform):
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clk_freq = 166666*1000
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
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self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
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default_subtarget = TestDesign
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