Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Build your hardware, easily!
34 Commits 42 Branches 14 Tags 30 MiB
C 52.7%
Python 43.6%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
Go to file
Florent Kermarrec b47153fbfa fix alignment (still some transmissions errors --> need to check clocks and resets) 2014-09-29 15:37:35 +02:00
lib/sata/k7sataphy fix alignment (still some transmissions errors --> need to check clocks and resets) 2014-09-29 15:37:35 +02:00
platforms modify TestDesign to be able to simulate phy with host <--> device loopback 2014-09-25 15:37:49 +02:00
sim add modelsim simulation and start fixing init 2014-09-26 17:05:05 +02:00
targets reorganize code 2014-09-27 15:34:28 +02:00
test init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
Makefile init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
README init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00

README 

             _____       _            ____  _     _ _       _ 
            |   __|___  |_|___ _ _   |    \|_|___|_| |_ ___| |
            |   __|   | | | . | | |  |  |  | | . | |  _| .'| |
            |_____|_|_|_| |___|_  |  |____/|_|_  |_|_| |__,|_|
                      |___|   |___|          |___|
 
 	Copyright 2014 / Florent Kermarrec / florent@enjoy-digital.fr
 
                        Kintex-7 SATA PHY for M-Labs
--------------------------------------------------------------------------------

[> Getting started
------------------
1. Obtain MiSoC and follow its "Quick start guide". Set the MSCDIR environment
  variable to the MiSoC directory.

2. Build design:
  make all
  
3. Load design:
  make load

4. Run test:
  make test

[> Cores :
  - UART2Wishbone bridge
  - SATA PHY

[> Contact
E-mail: florent@enjoy-digital.fr