Piotr Binkowski c02dd5e8f9 tools/litex_sim: add ddr4 PhySettings		2020-01-28 14:28:24 +01:00
..
boards	platforms/netv2: add pcie pins	2020-01-27 08:25:57 +01:00
build	build/xilinx/vivado: add pre_placement/pre_routing commands	2020-01-21 19:00:58 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	software/bios: revert M-Labs MiSoC copyright.	2020-01-27 13:12:37 +01:00
tools	tools/litex_sim: add ddr4 PhySettings	2020-01-28 14:28:24 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00