Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Build your hardware, easily!
11 Commits 37 Branches 13 Tags 47 MiB
C 53.1%
Python 43.2%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
Go to file
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist Convert -> convert 2012-01-05 19:27:45 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Initial import 2011-12-13 17:33:12 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py Convert -> convert 2012-01-05 19:27:45 +01:00