Franck Jullien b765bdf34e efinix: pll: allow output name to be changed		2021-09-21 14:23:00 +02:00
..
cores	efinix: pll: allow output name to be changed	2021-09-21 14:23:00 +02:00
doc	doc: Fix doc build with Sphinx v1.x	2021-02-04 09:40:04 +01:00
integration	soc/alloc_region: Ensure allocated Region is aligned on size.	2021-09-14 18:08:07 +02:00
interconnect	interconnect/wishbone: Specify Wishbone version (#999).	2021-09-08 17:33:01 +02:00
software	liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size.	2021-09-08 09:10:21 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00