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clock
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efinix: pll: allow output name to be changed
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2021-09-21 14:23:00 +02:00 |
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cpu
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cpu/vexriscv: Review/Cleanup #1022.
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2021-09-07 09:04:47 +02:00 |
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ram
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ram/lattice_nx: Add init parameter and rename method to add_init.
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2021-06-16 18:33:00 +02:00 |
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__init__.py
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compat: Add Retro-Compat for litex.soc.cores.up5kspram (that has now moved to litex.soc.cores.ram).
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2021-03-24 17:21:18 +01:00 |
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bitbang.py
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soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high).
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2020-11-10 09:46:43 +01:00 |
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code_8b10b.py
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soc/cores/code_8b10b: Minor cosmetic cleanups.
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2021-03-03 08:54:31 +01:00 |
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code_tmds.py
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cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.
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2021-03-04 19:32:41 +01:00 |
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dma.py
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soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader).
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2021-03-04 11:53:43 +01:00 |
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dna.py
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soc/cores/dna: Add separator/comment.
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2021-03-03 08:49:47 +01:00 |
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ecc.py
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soc/cores/ecc: Minor cosmetic cleanups.
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2021-03-03 08:55:37 +01:00 |
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emif.py
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soc: add SPDX License identifier and specify file is part of LiteX.
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2020-08-23 15:33:01 +02:00 |
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freqmeter.py
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soc/cores/freqmeter: Minor simplification.
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2021-06-01 10:26:27 +02:00 |
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gpio.py
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cores/gpio/GPIOIRQ: Add mode CSR (Edge or Change) and rename polarity CSR to edge.
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2021-03-20 21:49:12 +01:00 |
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i2s.py
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I2S fix: sample SYNC on the correct edge (#904)
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2021-05-07 08:17:49 +02:00 |
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icap.py
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soc/cores/icap: Minor cosmetic cleanups.
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2021-03-03 09:01:41 +01:00 |
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identifier.py
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soc: add SPDX License identifier and specify file is part of LiteX.
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2020-08-23 15:33:01 +02:00 |
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jtag.py
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jtag/jtagbone: Expose chain parameter.
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2021-05-06 14:58:47 +02:00 |
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led.py
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soc/cores/led: Minor cosmetic cleanups.
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2021-03-03 09:02:41 +01:00 |
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prbs.py
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cores/prbs: Minor Cleanup and make sure to generate errors when RX is Idle.
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2021-06-22 16:57:00 +02:00 |
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pwm.py
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soc/cores/pwm: add configurable default enable/width/period values.
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2021-02-18 09:39:18 +01:00 |
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spi.py
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cores/spi: Add Manual CS Mode (to allow doing Bulk Xfers without external changes), also cleanup/simplify a bit CSR descriptions.
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2021-06-18 10:07:01 +02:00 |
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spi_flash.py
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cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.
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2021-03-03 09:15:51 +01:00 |
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spi_opi.py
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breakout the keyclearb pin for integration elsewhere
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2021-06-11 04:44:39 +08:00 |
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timer.py
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cores/timer/uart: Use edge="rising on Timer/UART's EventSourceProcess.
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2021-05-27 18:47:40 +02:00 |
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uart.py
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Set TX UART pin high on reset
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2021-08-26 18:07:03 +02:00 |
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usb_fifo.py
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soc: add SPDX License identifier and specify file is part of LiteX.
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2020-08-23 15:33:01 +02:00 |
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usb_ohci.py
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soc/cores: Add initial USB OHCI core wrapper.
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2021-06-01 10:28:30 +02:00 |
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video.py
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cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes.
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2021-09-16 18:56:05 +02:00 |
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xadc.py
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cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.
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2021-03-15 10:35:10 +01:00 |
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