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b87ad1af63
litex
/
migen
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actorlib
History
Jannis Harder
f847faf004
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-14 21:25:19 +01:00
..
__init__.py
actorlib: Wishbone DMA read master (WIP)
2012-01-10 17:10:18 +01:00
crc.py
crc: generate error asynchronously to avoid stalling the flow and simplify
2014-11-01 21:21:46 +08:00
dma_lasmi.py
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
dma_wishbone.py
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
fifo.py
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-14 21:25:19 +01:00
misc.py
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
sim.py
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
spi.py
DMAWriteController: fix Demultiplexer layout
2014-10-20 23:58:16 +08:00
structuring.py
actorlib/structuring/Pipeline: make 'busy' a signal
2014-11-01 21:48:02 +08:00