litex/migen/fhdl
Sebastien Bourdeauducq a4782899f6 fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
bitcontainer.py migen/fhdl/bitcontainer: fix signed arrays (map is an iterator) 2013-12-10 23:32:12 +01:00
decorators.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
edif.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
module.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
namer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
simplify.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
specials.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
std.py fhdl.size: rename to bitcontainer 2013-12-03 22:51:52 +01:00
structure.py Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
tools.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
tracer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
verilog.py fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
visit.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00