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litex/migen
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Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 		2013-05-28 16:11:34 +02:00
..
actorlib Make memory ports part of specials 2013-05-28 16:11:34 +02:00
bank New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
bus Make memory ports part of specials 2013-05-28 16:11:34 +02:00
fhdl Make memory ports part of specials 2013-05-28 16:11:34 +02:00
flow New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
genlib Make memory ports part of specials 2013-05-28 16:11:34 +02:00
pytholite Make memory ports part of specials 2013-05-28 16:11:34 +02:00
sim New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00