Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials ... This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.		2013-05-28 16:11:34 +02:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
module.py	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
namer.py	New 'specials' API	2013-02-22 17:56:35 +01:00
size.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
specials.py	Make memory ports part of specials	2013-05-28 16:11:34 +02:00
std.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
structure.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
tools.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
visit.py	fhdl/visit: add TransformModule	2013-04-10 23:42:14 +02:00