Florent Kermarrec 0b3c4b50fa soc/cores/spi: add optional aligned mode. ... In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.		2020-04-22 13:15:51 +02:00
..
__init__.py
test_axi.py
test_bitbang.py
test_clock.py	soc/cores/clock: add CycloneVPLL.	2020-04-07 17:24:12 +02:00
test_code_8b10b.py
test_csr.py
test_ecc.py
test_emif.py	cores: add External Memory Interface (EMIF) Wishbone bridge.	2020-04-12 16:34:33 +02:00
test_gearbox.py
test_hyperbus.py
test_i2s.py
test_icap.py
test_packet.py
test_prbs.py
test_spi.py	soc/cores/spi: add optional aligned mode.	2020-04-22 13:15:51 +02:00
test_spi_opi.py
test_stream.py
test_targets.py	test/test_targets: remove versa_ecp3.	2020-03-25 08:47:43 +01:00