Michal Sieron bd82a7b888 build/xilinx/vivado: fix verilog include paths ... a286d77e introduced a bug, where `-include_dirs` parameter is incorrectly defined. Following TCL code is being generated: ```tcl synth_design -directive default -top digilent_arty -part xc7a35ticsg324-1L -include_dirs \{.join(self.platform.verilog_include_paths)}\} ``` Below is an explanation why it didn't work: Python's f-strings escape curly braces using double curly braces like so `{{` instead of using backslash `\{`. What's more, you need to alternate single and double quotations marks when using strings in curly braces expression otherwise two string objects are being generated and errors like this one can happen. Signed-off-by: Michal Sieron <msieron@antmicro.com>		2023-01-02 14:19:42 +01:00
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build	build/xilinx/vivado: fix verilog include paths	2023-01-02 14:19:42 +01:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/module: Add add/get_module methods to simplify user design and avoid direct use of setattr/getattr.	2022-12-08 14:20:38 +01:00
soc	Merge pull request #1548 from stone3311/master	2023-01-01 14:34:40 +01:00
tools	tools/litex_cli: Fix --write.	2022-12-12 11:26:37 +01:00
__init__.py	colorer: Avoid duplication and move it to litex/gen.	2022-11-03 09:49:51 +01:00