Florent Kermarrec e4f5dd987e interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.		2020-08-14 00:47:05 +02:00
..
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
avalon.py	interconnect/avalon: minor cleanup, remove max on SyncFIFO depth.	2020-07-08 07:53:42 +02:00
axi.py	soc/interconnect/axi: minor cleanups.	2020-08-05 12:11:28 +02:00
csr.py	interconnect/csr: add CSR registers ordering support.	2020-08-05 08:57:19 +02:00
csr_bus.py	interconnect/csr: add CSR registers ordering support.	2020-08-05 08:57:19 +02:00
csr_eventmanager.py	csr_eventmanager: add name and description args	2019-09-19 17:23:03 +08:00
packet.py	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
stream.py	interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.	2020-08-05 12:11:12 +02:00
stream_sim.py	add CONTRIBUTORS file and add copyright header to all files	2019-06-23 23:23:56 +02:00
wishbone.py	interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.	2020-08-14 00:47:05 +02:00