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c08687b9c6
litex
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migen
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Sebastien Bourdeauducq
c08687b9c6
bus/dfi: filter signals by direction
2012-02-15 21:48:05 +01:00
..
actorlib
Use enumerate(x) instead of zip(range(x), x)
2012-02-02 21:28:00 +01:00
bank
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
2012-02-15 18:23:31 +01:00
bus
bus/dfi: filter signals by direction
2012-02-15 21:48:05 +01:00
corelogic
Use double quotes for all strings
2012-02-14 13:12:43 +01:00
fhdl
fhdl: do not attempt slicing non-array signals to keep Verilog happy
2012-02-06 18:07:02 +01:00
flow
Use double quotes for all strings
2012-02-14 13:12:43 +01:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00