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0493212124
Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups
22 lines
681 B
Python
22 lines
681 B
Python
from migen.bus import wishbone
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from migen.bus import csr
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from migen.fhdl.structure import *
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from migen.corelogic import timeline
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class WB2CSR:
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def __init__(self):
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self.wishbone = wishbone.Interface()
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self.csr = csr.Interface()
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self.timeline = timeline.Timeline(self.wishbone.cyc & self.wishbone.stb,
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[(1, [self.csr.we.eq(self.wishbone.we)]),
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(2, [self.wishbone.ack.eq(1)]),
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(3, [self.wishbone.ack.eq(0)])])
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def get_fragment(self):
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sync = [
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self.csr.we.eq(0),
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self.csr.dat_w.eq(self.wishbone.dat_w[:8]),
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self.csr.adr.eq(self.wishbone.adr[:14]),
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self.wishbone.dat_r.eq(self.csr.dat_r)
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]
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return Fragment(sync=sync) + self.timeline.get_fragment()
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