Florent Kermarrec 175618bcb4 use csr_data_width of 32 to speed up data mila upload		2015-01-16 20:57:01 +01:00
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command	add frontend and improve BIST	2015-01-14 15:47:13 +01:00
frontend	add frontend and improve BIST	2015-01-14 15:47:13 +01:00
link	link/cont: improve timing	2015-01-16 18:13:07 +01:00
phy	use csr_data_width of 32 to speed up data mila upload	2015-01-16 20:57:01 +01:00
test	add frontend and improve BIST	2015-01-14 15:47:13 +01:00
transport	link: check CRC on RX path	2014-12-25 17:15:35 +01:00
__init__.py	add frontend and improve BIST	2015-01-14 15:47:13 +01:00
bist.py	bist: use hardware counter for speed calc and remove loops mode	2015-01-16 18:48:34 +01:00
common.py	add need_reset from controller to request system reset when SATA is not locked	2015-01-15 00:56:47 +01:00