Florent Kermarrec 7298fff1e6 soc/interconnect/stream_packet: fix Counter removing		2015-11-24 20:30:53 +01:00
..
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
csr.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
csr_bus.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
csr_eventmanager.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
dfi.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
dma_lasmi.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
lasmi_bus.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
stream.py	soc/interconnect/stream/SyncFIFO: expose fifo level	2015-11-16 16:11:31 +01:00
stream_packet.py	soc/interconnect/stream_packet: fix Counter removing	2015-11-24 20:30:53 +01:00
stream_sim.py	add TODOs	2015-11-14 03:15:10 +01:00
wishbone.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
wishbone2csr.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
wishbone2lasmi.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
wishbonebridge.py	soc/tools: initialize wishbone remote control (for now only uart)	2015-11-17 01:05:52 +01:00