Florent Kermarrec c27f24c4c0 reorganize code ... - use sys_clk of 166.66MHz and using it instead of sata clk. - rename clocking to CRG since it also handles resets. - create datapath and move code from gtx.		2014-09-27 15:34:28 +02:00
..
__init__.py	reorganize code	2014-09-27 15:34:28 +02:00
crg.py	reorganize code	2014-09-27 15:34:28 +02:00
ctrl.py	reorganize code	2014-09-27 15:34:28 +02:00
datapath.py	reorganize code	2014-09-27 15:34:28 +02:00
gtx.py	reorganize code	2014-09-27 15:34:28 +02:00
std.py	integrate phy in test design and start fix syntax errors	2014-09-24 16:07:34 +02:00