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litex/verilog/s6ddrphy
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Sebastien Bourdeauducq cdd58e023b s6ddrphy: use single-ended DQS 2012-02-17 10:53:58 +01:00
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patches s6ddrphy: use single-ended DQS 2012-02-17 10:53:58 +01:00
README s6ddrphy: prepare quilt 2012-02-14 15:52:39 +01:00

README 

The Verilog files of the Spartan-6 DDR PHY from Xilinx/Northwest Logic go here.