Florent Kermarrec cd6c04b24f soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx		2015-03-12 17:12:56 +01:00
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__init__.py	soc: do_exit is now provided by modules	2015-03-09 17:18:42 +01:00
cpuif.py	cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)	2015-03-02 16:52:17 +01:00
sdram.py	soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx	2015-03-12 17:12:56 +01:00