Florent Kermarrec c494ea231b cpu: Add initial NaxRiscv support (From out of tree prototyping in litex_naxriscv_test). ... - Supporting rv32ima for now. - No interrupt support yet. - AXI4 direct interfaces to LiteDRAM (fixed at 128-bit for now). - AXI4-Lite interfaces to LiteX main bus. - Pre-generated netlist used for now (need to allow customization/re-generation). - Running in simulation with: litex_sim --cpu-type=naxriscv - Running on hardware with: python3 -m litex_boards.targets.digilent_arty --cpu-type=naxriscv --build --load Demo with Linux and Doom on SDS1104X-E scope: https://twitter.com/enjoy_digital/status/1493996880593887235		2022-02-17 10:28:48 +01:00
..
build	build/xilinx/platform: Add specialized add_platform_command to handle yosys+nextpnr specificities.	2022-02-14 10:44:13 +01:00
compat	cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).	2022-01-07 19:08:03 +01:00
gen	soc/cores/jtag: Review/Cleanup JTAGTAPFSM and avoid specific CorrectedOngoingResetFSM.	2022-01-31 16:07:50 +01:00
soc	cpu: Add initial NaxRiscv support (From out of tree prototyping in litex_naxriscv_test).	2022-02-17 10:28:48 +01:00
tools	remote/comm_udp: Increase timeout.	2022-02-16 17:57:24 +01:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00