litex/migen/bus
Sebastien Bourdeauducq c4f4143591 New CSR API 2013-03-30 17:28:41 +01:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
csr.py New CSR API 2013-03-30 17:28:41 +01:00
dfi.py Remove Constant 2012-11-28 23:18:43 +01:00
memory.py sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
simple.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
transactions.py bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
wishbone.py sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
wishbone2asmi.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
wishbone2csr.py corelogic -> genlib 2013-02-22 23:19:37 +01:00