148 lines
4.4 KiB
Python
148 lines
4.4 KiB
Python
from functools import partial
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from migen.fhdl.structure import *
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from migen.corelogic import roundrobin, multimux
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from migen.bus.simple import Simple, get_sig_name
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_desc = [
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(True, "adr", 32),
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(True, "dat", 32),
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(False, "dat", 32),
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(True, "sel", 4),
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(True, "cyc", 1),
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(True, "stb", 1),
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(False, "ack", 1),
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(True, "we", 1),
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(True, "cti", 3),
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(True, "bte", 2),
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(False, "err", 1)
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]
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class Master(Simple):
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def __init__(self, name=""):
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Simple.__init__(self, _desc, False, name)
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class Slave(Simple):
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def __init__(self, name=""):
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Simple.__init__(self, _desc, True, name)
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class Arbiter:
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def __init__(self, masters, target):
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self.masters = masters
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self.target = target
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self.rr = roundrobin.Inst(len(self.masters))
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def get_fragment(self):
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comb = []
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# mux master->slave signals
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m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
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m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
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m2s_target = [getattr(self.target, name) for name in m2s_names]
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comb += multimux.multimux(self.rr.grant, m2s_masters, m2s_target)
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# connect slave->master signals
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s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
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for name in s2m_names:
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source = getattr(self.target, name)
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i = 0
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for m in self.masters:
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dest = getattr(m, name)
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if name == "ack_i" or name == "err_i":
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comb.append(dest.eq(source & (self.rr.grant == Constant(i, self.rr.grant.bv))))
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else:
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comb.append(dest.eq(source))
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i += 1
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# connect bus requests to round-robin selector
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reqs = [m.cyc_o for m in self.masters]
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comb.append(self.rr.request.eq(Cat(*reqs)))
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return Fragment(comb) + self.rr.get_fragment()
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class Decoder:
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# slaves is a list of pairs:
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# 0) structure.Constant defining address (always decoded on the upper bits)
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# Slaves can have differing numbers of address bits, but addresses
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# must not conflict.
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# 1) wishbone.Slave reference
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# Addresses are decoded from bit 31-offset and downwards.
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, offset=0, register=False):
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self.master = master
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self.slaves = slaves
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self.offset = offset
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self.register = register
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addresses = [slave[0] for slave in self.slaves]
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maxbits = max([bits_for(addr) for addr in addresses])
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def mkconst(x):
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if isinstance(x, int):
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return Constant(x, BV(maxbits))
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else:
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return x
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self.addresses = list(map(mkconst, addresses))
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ns = len(self.slaves)
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d = partial(declare_signal, self)
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d("_slave_sel", BV(ns))
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d("_slave_sel_r", BV(ns))
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def get_fragment(self):
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comb = []
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sync = []
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# decode slave addresses
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i = 0
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hi = self.master.adr_o.bv.width - self.offset
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for addr in self.addresses:
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comb.append(self._slave_sel[i].eq(
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self.master.adr_o[hi-addr.bv.width:hi] == addr))
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i += 1
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if self.register:
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sync.append(self._slave_sel_r.eq(self._slave_sel))
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else:
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comb.append(self._slave_sel_r.eq(self._slave_sel))
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# connect master->slaves signals except cyc
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m2s_names = [(get_sig_name(x, False), get_sig_name(x, True))
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for x in _desc if x[0] and x[1] != "cyc"]
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comb += [getattr(slave[1], name[1]).eq(getattr(self.master, name[0]))
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for name in m2s_names for slave in self.slaves]
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# combine cyc with slave selection signals
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i = 0
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for slave in self.slaves:
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comb.append(slave[1].cyc_i.eq(self.master.cyc_o & self._slave_sel[i]))
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i += 1
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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ackv = Constant(0)
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errv = Constant(0)
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for slave in self.slaves:
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ackv = ackv | slave[1].ack_o
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errv = errv | slave[1].err_o
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comb.append(self.master.ack_i.eq(ackv))
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comb.append(self.master.err_i.eq(errv))
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# mux (1-hot) slave data return
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i = 0
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datav = Constant(0, self.master.dat_i.bv)
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for slave in self.slaves:
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datav = datav | (Replicate(self._slave_sel_r[i], self.master.dat_i.bv.width) & slave[1].dat_o)
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i += 1
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comb.append(self.master.dat_i.eq(datav))
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return Fragment(comb, sync)
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class InterconnectShared:
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def __init__(self, masters, slaves, offset=0, register=False):
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self._shared = Master("shr")
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self._arbiter = Arbiter(masters, self._shared)
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self._decoder = Decoder(self._shared, slaves, offset, register)
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self.addresses = self._decoder.addresses
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def get_fragment(self):
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return self._arbiter.get_fragment() + self._decoder.get_fragment()
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