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Build your hardware, easily!
2 Commits 42 Branches 14 Tags 30 MiB
C 52.7%
Python 43.6%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
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Sebastien Bourdeauducq cd8544c758 Verilog generator 2011-12-04 22:26:32 +01:00
migen Verilog generator 2011-12-04 22:26:32 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
test.py Verilog generator 2011-12-04 22:26:32 +01:00