Rafal Kolucki cdd216f692 test/test_wishbone: Add basic test for SRAM with burst cycles support ... Tests incrementing address burst cycle with linear and wrapped increments. Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.		2022-04-12 14:06:22 +02:00
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__init__.py	…
test_axi.py	test/test_axi: Minor cleanups.	2022-02-17 15:13:05 +01:00
test_axi_lite.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_bitbang.py	…
test_clock.py	cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.	2022-01-25 11:09:15 +01:00
test_code_8b10b.py	…
test_cpu.py	litex_setup: Switch to manual install for Amaranth/Minerva (No longer supporting Python 3.6).	2022-04-04 15:39:05 +02:00
test_csr.py	soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).	2022-03-21 15:21:08 +01:00
test_ecc.py	…
test_emif.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_gearbox.py	…
test_hyperbus.py	soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.	2022-03-01 09:11:55 +01:00
test_i2s.py	…
test_icap.py	cores/icap/ICAP: Add Register read capability.	2021-10-04 17:22:57 +02:00
test_led.py	soc/cores/led: Review/Rework #1265.	2022-04-04 15:24:54 +02:00
test_packet.py	test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.	2021-10-23 17:40:41 +02:00
test_prbs.py	…
test_spi.py	…
test_spi_opi.py	…
test_stream.py	test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.	2021-10-23 17:40:41 +02:00
test_timer.py	test/test_timer: Update.	2021-05-27 19:37:51 +02:00
test_wishbone.py	test/test_wishbone: Add basic test for SRAM with burst cycles support	2022-04-12 14:06:22 +02:00